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MEDEA+ CMOS logic nanoscale projects

The EUREKA MEDEA+ Cluster is keeping the European microelectronics industry at the forefront of global technology producing silicon-based nanoscale devices. EUREKA partners are involved in a series of projects to develop basic fabrication processes for integrated circuits (ICs) to meet the demands for ever smaller and more highly performing electronic systems. These chips will make it possible for European companies to develop a wide range of new equipment - from versatile domestic multimedia equipment and highly effective automotive electronics, through improved medical diagnostic devices to ever more sophisticated digital cameras, mobile phones and portable entertainment terminals.

Complementary metal oxide semiconductor (CMOS) technology based on silicon wafers dominates chip manufacture. The energy efficiency of CMOS will continue to make it the technology of choice over the next decade for fabricating of microprocessor and memory chips, as well as application-specific ICs (ASICS) and complete system-on-chip (SoC) devices. Europe leads the world in ASICs and SoCs found in multimedia equipment, mobile phones, automotive systems and - increasingly - in medical devices.

The size of the smallest electronic circuit feature has long been expressed in microns, but continuous technology evolution means dimensions are now less than 100 nanometre (nm) or 1/10th of a micron - leading to the use of the term 'nanoelectronics' rather than 'microelectronics'. The classical laws of physics no longer apply at this level, giving away to quantum physics, which can provide a dramatic improvement in chip performance. However, fabrication processes for these chips need new materials, processes and equipment, all of which require a high level of research effort.

Close co-operation between national public authorities through EUREKA makes it possible to structure the appropriate support for successful European-wide projects. "The outstanding achievements of all these EUREKA projects are possible thanks to excellent collaboration between chipmakers, equipment suppliers, research institutes and academia," explains Guillermo Bomchil of STMicroelectronics.

EUREKA projects tend to focus on medium-short term issues.

Guillermo Bomchil, STMicroelectronics, France

Several EUREKA projects are contributing to the development of future nanometre CMOS generations. As a result of MEDEA+ work, 90-nm node technology is already in industrial production. The 65-nm node is reaching the product prototyping stage and first choices for a 45-nm technology are available with work continuing towards full process integration well in line with the International Technology Roadmap for Semiconductors (ITRS).

Industrial exploitation of 90-nm CMOS industrial technology is possible based on the rules for industrial fabrication developed in the MEDEA+ T201 CMOS logic 0.1 micrometre project.

In the year following the end of T201, 25 submicron circuits were processed at Crolles 2, the joint Freescale, Philips Semiconductors and STMicroelectronics pilot 300-mm wafer facility at Grenoble in France.

Work is already far beyond that achieved in the project itself. Products include digital, analogue, radio-frequency (RF) and embedded memory devices for diverse applications, such as wireless handsets, TV set-top boxes and networking components.

"In many cases, products had a 100% first-pass success rate, demonstrating design efficiency and optimum use of technology and manufacturing capabilities," says Bomchil. "And the achievements at 90 nm following the end of the MEDEA+ T201 project set the stage for successful 65-nm prototyping from the end of 2005." Project partners consider they have addressed many of the widely reported challenges with 90-nm technology and are applying the expertise to the next generations of devices.

Products had a 100% first-pass success rate, demonstrating design efficiency and optimum use of technology and manufacturing capabilities.

Subsequent EUREKA projects have set the scene for the future. The MEDEA+ T207 65 nm CMOS300 project that finished at the end of 2005 involved new substrate materials as well as multilevel interconnect metallisation for 65-nm circuit nodes. The 65-nm process has been established with significant yield improvements and reliability meeting specifications, and is now ready for the manufacture of prototype customer chips. The chipmaking partners will be sharing their 65-nm cell libraries and IP blocks and are confident about the success of the process for full production from 2008.

Looking further ahead to full CMOS integration at the 45-nm feature level, EUREKA will build on the outcome of the European Union NANOCMOS project. This achieved a first demonstration of feasibility of a suitable logic process in 2005, based on a selection of the most appropriate technology. The results are being exploited in the MEDEA+ second phase 2T103 FOREMOST project to keep Europe ahead of the ITRS, which calls for 45-nm node product shipments by 2010.

The main objective of the FOREMOST project is to demonstrate a full CMOS 45-nm process technology in European 300-mm manufacturing facilities. The proposal targets both CMOS logic and DRAM/flash memory process technologies, and promotes synergy between the competences of the Crolles 2 Alliance in Grenoble and Infineon in Dresden, Germany. It will demonstrate the feasibility of a complex test vehicle representing 45‑nm design rules that are three times more complex than the most complex current 90‑nm design. First validation should be by the end of 2007, with reliability data available in early 2008.

And EUREKA projects are already being planned to exploit the results of the EU Sixth Framework Programme (FP6) PULLNANO project that is looking further ahead at the needs for 32-/22-nm scale circuitry.

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