To develop a radiation immune flash memory chip.
The proposed project will consist of five phases. A bottom-up approach will be adopted by facing the problem at progressively higher levels of physical abstraction: i) material, ii) device, iii) circuit, iv) layout, v) architecture.
* Phase I. Test structures, such as memory cells, single transistors and elementary circuital blocks used in the memory integrated circuit, will be produced. Memory cells with two different local charge storage media will be produced: nitride and Si-nanodots.
* Phase II. Different characterisation techniques will be used in order to evaluate the performance and reliability of the test structures produced in the first phase:
- standard electrical characterisation;
- reliability accelerated tests;
- noise measurements;
- irradiation tests;
- SCM/AFM analysis;
The experimental results of this phase will be used to conduct successive sets of test structures with improved characteristics.
* Phase III. The design of a rad-hard memory integrated circuit will be undertaken by taking into account three aspects:
- radiation hardening by circuit design;
- radiation hardening by layout;
- radiation hardening by architecture.
* Phase IV. A prototype of the rad-hard memory integrated circuit designed in the third phase will be produced.
* Phase V. The functionality and the reliability of the memory chip prototype will be tested by using an auto diagnostic board.
- Tower Semiconductors, Israeli coordinator
- DEIS, University of Calabria, Italian coordinator
- RedCat Devices
- DTI, University of Milano
The partners ensure strong synergy and complementarily of their scientific expertise and planned activities. Most of the participants have successfully collaborated in the past in the form of joint publications and projects in the field of semiconductor devices and circuits.
Keywords: flash memory, radiation hardening, Si-nanodots, Integrated Circuit Layout.