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Reliable system level integration of stacked chips on mems

Restles will integrate serial technologies like silicon mems, wafer thinning, chip stacking and flip chip to one unique packaged chip stack at die scale (pcsds). The inherent cross influence of the different materials on device performance and intelligent control mechanisms to eliminate these parasitic effects will be investigated.

Start date: 
15-01-2007
Project Duration: 
53months
Technological Area: 
Electronic circuits, components and equipment
Market Area: 
Electronic Components

Raising the productivity and competitiveness of European businesses through technology. Boosting national economies on the international market, and strengthening the basis for sustainable prosperity and employment.