Mems / standard cmos integration: mesci phase ii

Development of mems-based embedded non-volatile memory integrated into cmos.

BACKGROUND AND MOTIVATION: R & D STRATEGY Micro Electro Mechanical Systems (MEMS) is a relatively new technology that has seen tremendous growth during the last decade. It allows the already mature electronic products to interface with the environment by means of sensors and actuators which form the dominating application field of MEMS today. CAVENDISH KINETICS decided to exploit the attractive features of MEMS technology and fabricate novel storage devices that are readily usable for the electronics industry. The motivation for this was that the ever shrinking size of electronic devices presents more and more difficulties to fabricate adequate embedded memory which is essential for the operation of ICs (Integrated Circuits) and microprocessors. On top of this, the electronics industry demands memory with ever increasing size, density and speed. CAVENDISH KINETICS has stepped away from the conventional memory development trends and approached the problem from a different angle: using tiny mechanical components as storage elements. This MEMS approach results in better memory device performance, better scalability for future process nodes, easier process integration and manufacturing, and hence lower production costs. Unfortunately the last decade has also shown that streamlining the fabrication processes of MEMS devices and electronic products is quite troublesome. A non-ideal 'workaround' is that the MEMS and the electronic IC are on two separate chips fabricated separately, which results in a compromise in device performance, a larger system and more power consumption. To avoid the compromise, a few years ago CAVENDISH KINETICS chose the path of fully integrating the MEMS devices into a standard CMOS (Complementary Metal-Oxide Silicon) process - which is the mainstream fabrication process of current electronic devices. The economic and market developments during the past few years has proven that this choice is a winner. Cavendish Kinetics is continuing along this path developing MEMS-based embedded memory products integrated into standard CMOS. The 'MESCI-II' research project builds on the results of the already completed 'MESCI-I' and 'MEDE' projects, and the 'Feasibility Study 1 MESCI-II' feasibility project. In these preceding projects the integrated MEMS/CMOS process technology in mainstream processes and a specific micro-encapsulation were developed. The technology platform was released under the name Nanomech(TM). The MESCI-II project aims to bring Nanomech to the cutting edge of deep sub-micron CMOS technology nodes. Besides embedded non-volatile memory (NVM) applications, this new development will also enable the production of standalone memory products, both in Aluminium and Copper based CMOS technology. PARTICIPANTS AND PROJECT ORGANISATION The goals set for the project will be achieved by setting up cooperation with a number of parties; all leaders in their own field. The project will be coordinated by CAVENDISH KINETICS, a specialist in MEMS and CMOS process development for NVM applications. The Nanomech technology platform, the NVM design and modelling (including both MEMS and CMOS) will be provided by CAVENDISH KINETICS B.V. and another partner. Implementing Nanomech in frontline processes will require researching new materials and fabrication processes. The new materials and new deposition processes will be provided by ASM, a leading supplier of semiconductor process equipment. ASM MICROCHEMISTRY will also provide Atomic Layer Deposition (ALD) technology to fabricate extremely thin films that are crucial for scaling down the memory devices to future technology nodes. The development will require specific analysis techniques. CALIPSO - a leader in Low Energy Ion Scattering (LEIS), which allows for analysis of the topmost atomic layer will contribute with surface analysis and material science consulting. The best material candidates will be utilised in the extended Nanomech technology and integrated into the process flow at the process development site. The primary process development site will be the INSTITUTE FOR MICROELECTRONICS (IME) in SINGAPORE. IME is a very advanced 8-inch CMOS/MEMS R & D facility providing unique process combinations. Test structures will be fabricated here based on the new ultra thin films. Note: With the addition of SVTC as a service partner, the primary development site has been switched from IME to SVTC. The main reasons for doing this switch have been the requirement to add new materials to the research phase of the project as well as the ability to move down to geometries below 0.18 nanometres. In addition, the other advantages are the increased support and expertise available for the development phase of the project where the developed process will be integrated into front-line technologies such as 130 and 90 nanometres. All the above is not available at IME. Already in April we had to conclude that with the given set-up, a significant amount of work scheduled for IME would have to be outsourced to other companies because of the missing capabilities at IME.
Project ID: 
3 709
Start date: 
Project Duration: 
Project costs: 
2 190 000.00€
Technological Area: 
Market Area: 
Electronic Components

Raising the productivity and competitiveness of European businesses through technology. Boosting national economies on the international market, and strengthening the basis for sustainable prosperity and employment.